ASIC emulation
Pre-silicon validation + bitstream signature
FPGA runs the target design, CPU orchestrates testbenches, GPU for coverage simulation.
FPGA
RTL emulation + signature
Workloads
- ▸ Pre-tape-out design
- ▸ ML-DSA bitstream signature
- ▸ Cycle attestation
Performance
×1 000 speedup vs RTL sim
CPU
Testbench + regression
Workloads
- ▸ UVM testbench
- ▸ Nightly regression
- ▸ Bug triage + Jira
Performance
10 k tests / night
GPU
Coverage + fuzzing
Workloads
- ▸ Massive stimulus fuzzing
- ▸ Parallel coverage closure
- ▸ Auxiliary formal
Performance
99 % coverage in 48 h
Multi-agent scenario
A new bitstream is loaded: CPU launches regression, FPGA runs RTL at full speed, GPU fuzzes inputs, final signature is sealed by GARANCE before archiving.